Information, such as information associated with data packets, can be stored in a memory unit that includes multiple interleaved memory banks. For example, FIG. 1 is a block diagram of a known network device 100 that includes a network processor 110 that can transmit and receive data packets via a communication unit 120. The network processor 110 also stores and retrieves information associated with the data packets via a memory unit 130 that includes four interleaved memory banks 132 (i.e., banks 0 through 3). The use of interleaved memory banks 132 may facilitate concurrency and bandwidth utilization in the network device 100. The memory banks 132 may be, for example, Dynamic Random Access Memory (DRAM) devices.
A memory controller 140 facilitates the exchange of information between the network processor 110 and the memory unit 130. For example, the network processor 110 might issue to the memory controller 140 a command to read a particular data packet. The memory controller 140 would in turn retrieve the appropriate information from the memory unit 130. In particular, the memory controller 140 would accesses the information via a row 134 (that spans the four memory banks 132) and a column that defines a position within that row 134.
The memory controller 140 may access the memory unit 130 in accordance with a pre-defined memory protocol. For example, FIG. 2 is a flow chart of a known method to exchange information with a memory unit 130 associated with DRAM devices. Note that a DRAM device stores each bit of information in a “cell” composed of a capacitor and a transistor. Because the capacitor in a DRAM cell can hold a charge for only a brief period of time, the DRAM device is continually refreshed in order to retain the data.
When the memory controller 140 needs to access information (i.e., to store or retrieve information), it issues a pre-charge to the memory unit at 202. This flushes out the previously active row. The memory controller 140 then issues a Row Address Strobe (RAS) to the memory unit 130 for the appropriate row at 204. The RAS initiates the memory cycle and latches the row address (i.e., the address pins are latched when the RAS is received by the memory unit 130). At 206, the memory controller 140 issues a Column Address Strobe (CAS) to the memory unit 130 for the appropriate column. The CAS latches the column address and initiates the read or write operation. At 208, the appropriate data is exchanged with the memory unit 130 (i.e., the data is stored into or read from the appropriate row and column).
If the next access to the memory unit 130 is for the same row, a CAS for the next column can simply be issued at 206 and the process continues. That is, no pre-charge or RAS needs to be issued to flush the currently active row. If, however, the next access to the memory unit 130 is for a different row, a pre-charge and RAS must be issued for the new row at 202 and 204 before the process continues.
Note that a memory controller 140 might issue a pre-charge and a RAS to a particular memory bank 132 even when the same row is being accessed. For example, the memory controller 140 might not store an indication of the last row that was accessed and/or might issue the pre-charge as soon as the network processor 110 requests access to a memory bank 132.
Because of this protocol, there is a delay-between the time information in a particular memory bank 132 is accessed and the next time the same memory bank 132 can be accessed. That is, if the network processor 110 repeatedly accesses information stored in the same memory bank 132, significant delays can be incurred (even when the information is stored in a single row).
Consider, for example, a network processor 110 that sequentially accesses a series of data packets that are sequentially stored in the memory unit 130. In this case, a particular memory bank 132 might be accessed before a prior access to that memory bank 132 is completed. As a result, the second access can experience a significant delay, and the overall performance of the network device 100 can be degraded.